A new algorithm for factorization of logic expressions

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1996.Includes bibliographical references (leaves 53-54).by Farzan Fallah.M.S

Wind farm reactive power optimization by using imperialist competitive algorithm

In this paper a new evolutionary computing method based on imperialist competitive algorithm (ICA) is used for optimization of the reactive power in a wind farm. The output power and also the reactive power of wind farms are not constant due to the oscillation in wind speed. Reactive power optimization is known as an efficient way to have an improvement in power quality and also to reduce power loss. The conventional optimization algorithms have some drawbacks, such as slow convergence and premature. ICA as one of the newest optimization algorithm could be applied in order to optimization of the reactive power and overcomes the difficulties which are coming from the traditional methods. In this paper, the reactive power consumption of a wind turbine is optimized by using (ICA) method. To illustrate the application of the method, a wind farm with some uncertainties is provided. Finally the results of the ICA method are compared with the one of conventional method. Results show that the proposed reactive power optimization method is simple and effective

PID controller adjustment for MA-LFC by using a hybrid genetic-tabu search algorithm

In this paper a hybrid Genetic-Tabu Search Algorithm (GT) is used for tuning the elements of a PID controller which is applied in a Multi Area Load Frequency Control System (MA-LFC). If a large power imbalance is suddenly happened in a multi area power electric system, generation units and also consumer sides will be affected by the distortion in the energy balance between both two sides. This inequality is firstly handled by the kinetic energy of the system turning components, but, eventually, the frequency will change. Therefore, LFC is considered as one of the most challenging issues in power system control and operation. PID type controllers are conventional solutions for MA-LFC. The three parameters of the PID controllers have been adjusted traditionally. In this paper, a PID controller is applied for the MA-LFC problem and then its parts are modified by using GT method. To validate the application of the technique, a multi area network with some uncertainties is provided. Finally the results of the GT-PID controller are compared with the ones of GA optimized controllers. The simulation results show the success and the validity of the GT-PID controller in compare with the GA - PID controller

Custom Integrated Circuits

Contains table of contents for Part III, table of contents for Section 1 and reports on eleven research projects.IBM CorporationMIT School of EngineeringNational Science Foundation Grant MIP 94-23221Defense Advanced Research Projects Agency/U.S. Army Intelligence Center Contract DABT63-94-C-0053Mitsubishi CorporationNational Science Foundation Young Investigator Award Fellowship MIP 92-58376Joint Industry Program on Offshore Structure AnalysisAnalog DevicesDefense Advanced Research Projects AgencyCadence Design SystemsMAFET ConsortiumConsortium for Superconducting ElectronicsNational Defense Science and Engineering Graduate FellowshipDigital Equipment CorporationMIT Lincoln LaboratorySemiconductor Research CorporationMultiuniversity Research IntiativeNational Science Foundatio

Coverage-directed validation of hardware models

Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999.Includes bibliographical references (leaves 157-160 ).With the rapid increase in the number of transistors that can be fabricated on a single chip, digital systems have become very complex. The increase in the complexity of the digital systems, and the desire to achieve faster time-to-market has made the use of the Computer-Aided Design (CAD) tools indispensable. Designers typically start with writing behavioral or Register-Transfer level (RTL) description of the system functionality using a Hardware Description Language (HDL). After that they transform the HDL description to the gate-level, transistor level, and finally generate mask-level layout which is used to manufacture the chip. CAD tools are used extensively to execute transformations between different levels of abstraction. They also help to optimize the design so as to achieve better performance and meet different constraints relating to speed, power consumption, and area. In order to have a working chip, the designer has to make sure that the original HDL description is correct and also that no error is introduced during transformations to the lower levels. Currently validation of the initial HDL description and verifying the design in different levels of abstraction against each other is a major bottleneck in the design process. Because the HDL description is usually the first description of the design, simulation is the primary methodology for validating it. Simulation-based verification is necessarily incomplete because it is not computationally feasible to exhaustively simulate designs. It is important therefore to quantitatively measure the degree of verification coverage of the design. Simulation-based validation has suffered from a disconnect between the metrics used to measure the coverage of a set of simulation vectors and the vector generation process. This disconnect has resulted in the simulation of virtually endless streams of vectors which achieve enhanced coverage only infrequently. Another drawback has been that most coverage metrics proposed have either been too simplistic or too inefficient to compute. This thesis provides the details of an efficient method to compute an Observability-based Code COverage Metric (OCCOM) that can be used while simulating complex HDL designs. It also introduces a new method for generating test vectors under any coverage metric. In this thesis the problem of generating test vectors for both combinational and sequential circuits under OCCOM is discussed. A prototype system which generates test vectors under the OCCOM coverage metric has been built. The system can be used during the design process, as well as during post-design debugging to validate the initial HDL description.by Farzan Fallah.Ph.D

Q[damaged area -- whole fields] ::> [Diagnosis = Anthracnose] D13: Q([time = Apr... Jul] [precipitation >_ n] [leaves = abn] (leafspots halos -- no yellow halosl[leafspots watersoaked margin = abs] (leafspot size> /s inch](leaf shredding = p]) + O([damage

This paper addresses the problem of low-power fanout optimization. We show that due to neglecting short-circuit current, previous analytical techniques proposed to optimize the area of a fanout tree may result in excessive power consumption. This shows to achieve a low-power fanout tree, an accurate power consumption model should be used as the objective function. Moreover, we propose an efficient method to minimize the total power consumption of a fanout tree by using MTCMOS and Multi-Vt techniques. Experimental results show that depending on the activity factor of the circuit, the proposed technique can reduce the power consumption of the fanout tree 18 % to 45%

Runtime Mechanisms for Leakage Current Reduction in CMOS VLSI Circuits

This paper describes two runtime mechanisms for reducing the leakage current of a CMOS circuit. In both cases, it is assumed that the system or environment produces a "sleep" signal that can be used to indicate that the circuit is in a standby mode. In the first method, the "sleep" signal is used to shift in a new set of external inputs and pre-selected internal signals into the circuit with the goal of setting the logic values of all of the internal signals so as to minimize the total leakage current in the circuit. This minimization is possible because the leakage current of a CMOS gate is a strong function of the input combination applied to its inputs. In the second method, NMOS and PMOS transistors are added to some of the gates in the circuit to increase the controllability of the internal signals of the circuit and decrease the leakage current of the gates using the "stack effect". This is, however, done carefully so that the minimum leakage is achieved subject to a delay constraint for all input-output paths in the circuit. In both cases, Boolean satisfiability is used to formulate the problems, which are subsequently solved by employing a highly efficient SAT solver. Experimental results on the circuits in the MCNC91 benchmark suite demonstrate that it is possible to reduce the leakage current by up to 70% in VLSI circuits at the expense of a very small overhead